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Features
* * * * * * * * * * *
PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors High Temperature Capability up to 200 C Junction A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply the Gate of the External Battery Reverse Protection NMOS 5V/3.3V Regulator and Current Limitation Function Reset Derived From 5V/3.3V Regulator Output Voltage A Programmable Window Watchdog Battery Overvoltage Protection and Battery Undervoltage Management Overtemperature Warning and Protection (Shutdown) High Voltage Serial Interface for Communication QFN32 Package
1. Description
The ATA6824 is designed for DC motor control application in automotive high temperature environment like in mechatronic assemblies in the vicinity of the hot engine, e.g. turbo charger. With a maximum junction temperature of 200C, ATA6824 is suitable for applications with an ambient temperature up to 150C. The IC includes 4 driver stages to control 4 external power MOSFETs. An external microcontroller provides the direction signal and the PWM frequency. In PWM operation, the high-side switches are permanently on while the low-side switches are activated by the PWM frequency. ATA6824 contains a voltage regulator to supply the microcontroller; via the input pin VMODE the output voltage can be set to 5V or 3.3V respectively. The on-chip window watchdog timer provides a pin-programmable time window. The watchdog is internally trimmed to an accuracy of 10% SPI with a maximum data rate of 20 kBaud.
High Temperature H-bridge Motor Driver ATA6824
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Figure 1-1.
Block Diagram
M
CVRES
CP VRES CPLO RGATE H2 RGATE H1 S1 S2 RGATE L1 RGATE L2 PGND GND Charge Pump CPIH OT UV 12V Regulator Supervisor DG2 DG1 CC CC timer HS Driver 2 HS Driver 1 LS Driver 1 LS Driver 2 VBAT DG3
CCP
CVG
VBAT
VG
PBAT VINT Vint 5V Regulator
OTP 12 bit
OV
Logic Control
Oscillator
CCC RCC
CVINT
CP
WD timer
VBAT TP1 VBG VBATSW VCC 5V Regulator Serial Interface
RRWD
SIO
Bandgap
CSIO
WD TP2 DIR PWM RX TX
VCC
VMODE
/RESET
CVCC
Battery
Microcontroller
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2. Pin Configuration
Figure 2-1. Pinning QFN32
TP2 VBATSW VBAT VCC PGND L1 L2 PBAT VMODE VINT RWD CC /RESET WD GND SIO 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 Atmel YWW 21 ATA6824 20 ZZZZZ-AL 19 18 17 9 10 11 12 13 14 15 16 TX DIR PWM TP1 RX DG3 DG2 DG1 VG CPLO CPHI VRES H2 S2 H1 S1
Note:
YWW ATA6824 ZZZZZ AL
Date code (Y = Year - above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Pin Description
Symbol VMODE VINT RWD CC /RESET WD GND SIO TX DIR PWM TP1 RX DG3 DG2 DG1 S1 H1 S2 H2 VRES I/O I I/O I I/O O I I I/O I I I - O O O O I/O O I/O O I/O Function Selector for VCC and interface logic voltage level Blocking capacitor 220 nF/10V/X7R Resistor defining the watchdog interval RC combination to adjust cross conduction time Reset signal for microcontroller Watchdog trigger signal Ground for chip core High Voltage (HV) serial interface Transmit signal to serial interface from microcontroller Defines the rotation direction for the motor PWM input controls motor speed Test pin to be connected to GND Receive signal from serial interface for microcontroller Diagnostic output 3 Diagnostic output 2 Diagnostic output 1 Source voltage H-bridge, high-side 1 Gate voltage H-bridge, high-side 1 Source voltage H-bridge, high-side 2 Gate voltage H-bridge, high-side 2 Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R
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Table 2-1.
Pin 22 23 24 25 26 27 28 29 30 31 32
Pin Description (Continued)
Symbol CPHI CPLO VG PBAT L2 L1 PGND VCC VBAT VBATSW TP2 I/O I O I/O I O O I O I O - Function Charge pump capacitor 220 nF/25V/X7R Blocking capacitor 470 nF/25V/X7R Power supply (after reverse protection) for charge pump and H-bridge Gate voltage H-bridge, low-side 2 Gate voltage H-bridge, low-side 1 Power ground for H-bridge and charge pump 5V/100 mA supply for microcontroller, blocking capacitor 2.2 F/10V/X7R Supply voltage for IC core (after reverse protection) 100 PMOS switch from VBAT Test pin to be connected to GND
3. General Statement and Conventions
* Parameter values given without tolerances are indicative only and not to be tested in production * Parameters given with tolerances but without a parameter number in the first column of parameter table are "guaranteed by design" (mainly covered by measurement of other specified parameters). These parameters are not to be tested in production. The tolerances are given if the knowledge of the parameter tolerances is important for the application * The lowest power supply voltage is named GND * All voltage specifications are referred to GND if not otherwise stated * Sinking current means that the current is flowing into the pin (value is positive) * Sourcing current means that the current is flowing out of the pin (value is negative)
3.1
Related Documents
* Qualification of integrated circuits according to Atmel(R) HNO procedure based on AEC-Q100 * AEC-Q100-004 and JESD78 (Latch-up) * ESD STM 5.1-1998 * CEI 801-2 (only for information regarding ESD requirements of the PCB)
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4. Application
4.1 General Remark
This chapter describes the principal application for which the ATA6824 was designed. Because Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given.
Table 4-1.
Component CVINT CVCC CCC RCC CVG CCP CVRES RRWD CSIO
Typical External Components (See also Figure 1-1 on page 2)
Function Blocking capacitor at VINT Blocking capacitor at VCC Cross conduction time definition capacitor Cross conduction time definition resistor Blocking capacitor at VG Charge pump capacitor Reservoir capacitor Watchdog time definition resistor Filter capacitor for serial interface Value 220 nF, 10V, X7R 2.2 F, 10V, X7R Typical 330 pF, 100V, COG Typical 10 k 470 nF, 25V, X7R 220 nF, 25V, X7R 470 nF, 25V, X7R Typical 51 k Typical 220 pF, 100V 10% 10% 10% 1% 10% Tolerance 10% 10%
5. Functional Description
5.1
5.1.1
Power Supply Unit with Supervisor Functions
Power Supply The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT pin of the IC (see Figure 1-1 on page 2). An internal low-power and low drop regulator (VINT), stabilized by an external blocking capacitor, provides the necessary low-voltage supply for all internal blocks except the digital IO pins. This voltage is also needed in the wake-up process. The low-power band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks are supplied by the internal regulator.
Note: The internal supply voltage VINT must not be used for any other supply purpose!
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator. A power-good comparator checks the output voltage of the VINT regulator and keeps the whole chip in reset as long as the voltage is too low. There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset. The signal can be used to switch on external voltage regulators, etc.
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5.1.2
Voltage Supervisor This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it. Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz.
5.1.3
Temperature Supervisor There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry and to protect the external NMOSFET transistors. In case of detected overtemperature (180C), the diagnostic pin DG3 will be switched to "H" to signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (200C), the VCC regulator and all drivers including the serial interface will be switched OFF immediately and /RESET will go LOW. Both temperature thresholds are correlated. The absolute tolerance is 15C and there is a built-in hysteresis of about 10K to avoid fast oscillations. After cooling down below the 170C threshold; the IC will go into Active mode.
5.2
5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 F ceramic capacitor for stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage. The output voltage accuracy is in general < 3%; in the 5V mode with VVBAT < 8V it is limited to < 5%. To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 160 mA to 320 mA. The delivered voltage will break down and a reset may occur. Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink. A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low.
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Figure 5-1. Correlation between VCC Output Voltage and Reset Threshold
5.15V 4.9V VCC1 4.85V VtHRESH 4.1V
VCC1-VtHRESH = VCC1 - VtHRESH
The voltage difference between the regulator output voltage and the upper reset threshold voltage is bigger than 100 mV.
5.3
Reset and Watchdog Management
The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is adjustable via the external resistor RWD. The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time window of TWD.
Figure 5-2.
Timing Diagram of the Watchdog Function
tres tresshort
/RESET td t1 t2 t1 t2 td
WD
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5.3.1
Timing Sequence For example, with an external resistor RWD = 33 k 1% we get the following typical parameters of the watchdog. TOSC = 12.32 s, t1 = 12.1 ms, t2 = 9.61 ms, TWD = 16.88 ms 10% The times tres = 68 ms and td = 68 ms are fixed values with a tolerance of 10%. After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low for the time tres (typically 68 ms), then switches to high. For an initial lead time td (typically 68 ms for setups in the controller) the watchdog waits for a rising edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the watchdog will reset the microcontroller for tres and wait td for the rising edge on WD. Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the timeframe of t2 = 9.61 ms. The trigger event will restart the watchdog sequence. Figure 5-3. TWD versus RWD
60
50 max
typ
TWD (ms)
40
30 min 20
10
0 10 20 30 40 50 60 70 80 90 100
RWD (k)
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms. The watchdog start sequence is similar to the power-on reset. The internal oscillator is trimmed to a tolerance of < 10%. This means that t1 and t2 can also vary by 10%. The following calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide. t1min = 0.90 x t1 = 10.87 ms, t1max = 1.10 x t1 = 13.28 ms t2min = 0.90 x t2 = 8.65ms, t2max = 1.10 x t2 = 10.57 ms Twdmax = t1min + t2min = 10.87 ms + 8.65 ms = 19.52 ms Twdmin = t1max = 13.28 ms Twd = 16.42 ms 3.15 ms (19.1%) Figure 5-3 on page 8 shows the typical watchdog period TWD depending on the value of the external resistor ROSC. A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth).
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5.4 High Voltage Serial Interface
A bi-directional bus interface is implemented for data transfer between hostcontroller and the local microcontroller (SIO). The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shaping, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver. In case of an active reset shown at pin /RESET the pin SIO is switched to low. 5.4.1 Transmit Mode During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin SIO. The pin TXD has a pull-down resistor included. To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave-shaping unit. Transmission will be interrupted in the following cases: * Thermal shutdown active Figure 5-4. Definition of Bus Timing Parameters
tBit TXD
(input to transmitting Node)
tBit
tBit
tBus_dom(max)
tBus_rec(min)
THRec(max) VS
(Transceiver supply of transmitting node)
Thresholds of receiving node 1 SIO Bus Signal
THDom(max) Thresholds of receiving node 2
THRec(min) THDom(min)
tBus_dom(min) RXD
(output of receiving Node 1)
tBus_rec(max)
trx_pdf(1) RXD
(output of receiving Node 2)
trx_pdr(1)
trx_pdr(2)
trx_pdf(2)
The recessive BUS level is generated from the integrated 30 k pull-up resistor in series with an active diode. This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS > VSUP).
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5.5
5.5.1
Control Inputs DIR and PWM
Pin DIR Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is included.
5.5.2
Pin PWM Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included.
Table 5-1.
ON 0 1 1 DIR X 0 1
Status of the IC Depending on Control Inputs and Detected Failures
Driver Stage for External Power MOS H1 OFF ON /PWM L1 OFF OFF PWM H2 OFF /PWM ON L2 OFF PWM OFF Standby mode Motor PWM forward Motor PWM reverse X PWM PWM Comments PWM
Control Inputs
The internal signal ON is high when * At least one valid trigger has been accepted (SYNC = 1) * VBAT is inside the specified range (UV = 0 and nOV = 1) * The charge pump has reached its minimum voltage (CPOK = 1) and * The device is not overheated (OT2 = 0) In case of a short circuit, the appropriate transistor is switched off after a debounce time of about 10 s. In order to avoid cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC combination.
Table 5-2.
CPOK 0 X X X X Note:
Status of the Diagnostic Outputs
Device Status OT1 X 1 X X OV X X 1 X UV X X X 1 SC X X X X Diagnostic Outputs DG1 - - - - DG2 1 - 1 1 - DG3 - 1 - - - Charge pump failure Overtemperature warning Overvoltage Undervoltage Short circuit Comments
X X X 1 1 X represents: don't care - no effect) OT1: Overtemperature warning OV: Overvoltage of VBAT UV: Undervoltage of VBAT SC: Short circuit CPOK: Charge pump OK
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5.6 VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage is reduced if the supply voltage at VBAT falls below 12V.
5.7
Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the output voltage on the reservoir capacitor is VBAT plus VG. The charge pump is clocked with a dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC level.
5.8
Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning level will be reached at 180C. At this point the IC stays fully functional and a warning will be sent to the microcontroller. At junction temperature 200C the VCC regulator will be switched off and a reset occurs.
5.9
H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side drivers and two push-pull drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and logic-level power NMOS. The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is possible to control the external load (motor) in the forward and reverse direction (see Table 5-1 on page 10). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in both directions.
5.9.1
Cross Conduction Time To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in the following way: tCC (s) = 0.41 x RCC (k) x CCC (nF) (tolerance: 5% 0.15 s) The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level. The resistor RCC must be greater than 5 k and should be as close as possible to 10 k, the CCC value has to be 5 nF. Use of COG capacitor material is recommended. The time measurement is triggered by the PWM or DIR signal crossing the 50% level.
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Figure 5-5.
Timing of the Drivers
PWM or DIR
50%
t
tLxHL tLxf tLxLH tLxr
80%
Lx
20%
tCC
t
tHxLH tHxr tHxHL tHxf
tCC
80%
Hx
20%
t
The delays tHxLH and tLxLH include the cross conduction time tCC.
5.10
Short Circuit Detection
To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS. If the transistors are switched ON and the source-drain voltage difference is higher than the value VSC (4V with tolerances) for a time > tSC (typically 10 s) the signal SC (short circuit) will be set and the drivers will be switched off immediately. The diagnostic pin DG1 will be set to "H". With the next transition on pin PWM, the bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on again. There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time > tSC the drivers will be switched off immediately and DG1 will be set to "H". It will be cleared as above.
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6. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description Ground Power ground Reverse protected battery voltage Reverse protected battery voltage Digital output Digital output 4.9V output, external blocking capacitor Cross conduction time capacitor/resistor combination Digital input coming from microcontroller Watchdog timing resistor Digital input direction control Digital input PWM control + Test mode 5V regulator output Digital input 12V output, external blocking capacitor Digital output Digital input Serial interface data pin Source external high-side NMOS Gates external low-side NMOS Gates of external high-side NMOS Charge pump Charge pump Charge pump output Switched VBAT Power dissipation Storage temperature Soldering temperature (10s) Notes: 1. For VVBAT 13.5V 2. May be additionally limited by external thermal resistance Pin Name GND PGND VBAT PBAT /RESET DG1, DG2, DG3 VINT CC WD RWD DIR PWM VCC VMODE VG RX TX SIO S1, S2 L1, L2 H1, H2 CPLO CPHI VRES VBATSW Ptot STORE SOLDERING -55 Min 0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -27
(1)
Max 0 +0.3 +40 +40 VVCC + 0.3 VVCC + 0.3 +5.5 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 +5.5 VVINT + 0.3 +16 VVCC + 0.3 VVCC + 0.3 VVBAT + 2 +30 VVG + 0.3 VS + 16 VPBAT + 0.3 VVRES + 0.3 +30 VVBAT + 0.3 1.4
(2)
Unit V V V V V V V V V V V V V V V V V V V V V V V V V W C C
-2 VPGND - 0.3 VS - 1 -0.3 -0.3 -0.3 -0.3
+200 240
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7. Thermal Resistance
Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient when heat slug is soldered to PCB Symbol Rthjc Rthja Value <5 25 Unit K/W K/W
8. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly. Parameters Operating supply voltage Operating supply voltage
(1) (2)
Symbol VVBAT1 VVBAT2 VVBAT3 VVBAT4 VVBAT5 Tj Ta Ta Ta
Min 7 6 4.5 0 > 20 -40 -40 180 200
Max 18 <7 <6 < 4.5 40 +200 +150 200 220
Unit V V V V V C C C C
Operating supply voltage(3) Operating supply voltage(4) Operating supply voltage Normal functionality Normal functionality, overtemperature warning Drivers for H1, H2, L1, L2, and SIO are switched OFF, VCC regulator is OFF Note: 1. Full functionality
(5)
Junction temperature range under bias
2. H-bridge drivers may be switched off (undervoltage detection) 3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly 4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct 5. H-bridge drivers are switched off
9. Noise and Surge Immunity
Parameters Conducted interferences Interference suppression ESD (Human Body Model) CDM (Charge Device Model) Note: 1. Test pulse 5: Vvbmax = 40V Test Conditions ISO 7637-1 IEC-CISPR25 ESD S 5.1 ESD STM5.3. Value Level 4(1) Level 5 2 kV 500V
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10. Electrical Characteristics
All parameters given are valid for 7V VBAT 18V and for -40C ambient 150C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max 1 Power Supply and Supervisor Functions 25, 30 IVBAT1 7 1.1 Current consumption VBAT VVBAT = 13.5V(1) 1.2 Internal power supply 2 VINT 4.8 4.94 5.1 1.235 1.3 Band gap voltage VBG Overvoltage threshold 1.4 30 VTHOV 19.8 22.3 VBAT Overvoltage threshold 30 VTOVhys 1 2 1.5 hysteresis VBAT Undervoltage threshold 30 VTHUV 6.5 7 1.6 VBAT Measured during Undervoltage threshold 0.2 0.4 30 VTUVhys 1.7 qualification only hysteresis VBAT On resistance of VBAT 31 RON_VBATSW 100 VVBAT = 13.5V 1.8 switch 2 5V/3.3V Regulator 9V < VVBAT < 40V, 2.1 Regulated output voltage 4.85 (3.2) 5.15 (3.4) 29 VCC1 Iload = 0 mA to 100 mA 9V < VVBAT < 40V, 2.1a Regulated output voltage Iload = 0 mA to 80 mA, 29 VCC1 4.85 (3.2) 5.15 (3.4) Ta > 125C 6V < VVBAT 9V 2.2 Regulated output voltage 4.75 (3.2) 5.25 (3.4) 29 VCC2 Iload = 0 mA to 100 mA DC line 29 <1 50 2.3 Line regulation Iload = 0 mA to 100 mA regulation DC load 2.4 Load regulation Iload = 0 mA to 100 mA 29 <10 50 regulation 2.5 Output current limitation VVBAT > 6V 29 IOS1 100 300 Serial inductance to CVCC 2.6 29 ESL 1 20 including PCB Serial resistance to CVCC 29 ESR 0 0.5 2.7 including PCB (2), (3) 29 CVCC 1.5 3.0 2.8 Blocking cap at VCC 2.9 HIGH threshold VMODE 1 VMODE H 4.0 2.10 LOW threshold VMODE 1 VMODE L 0.7 * Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on T100; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc 11. See Figure 5-4 on page 9 "Definition of Bus Timing Parameters" Unit mA V V V V V V Type* A A A A A A A A
V V V mV mV mA nH F V V
A A A A A C D D D A A
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10. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 150C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max 3 VG Regulator = PBAT = 14V V 24 VVG 3.1 Regulated output voltage BAT 11.9 13 Imax = 20 mA = PBAT = 9V V 24 VVG 7.0 9.0 3.2 Regulated output voltage BAT Imax = 20 mA 4 Reset and Watchdog VCC threshold voltage VMODE = "H" 4.1 4.9 (3.25) 29 VtHRESH level for /RESET (VMODE = "L") Tracking of reset 100 VMODE = "H" 4.1a thres-hold with regulated 29 VVCC1-VtHRESH (70) (VMODE = "L") output voltage VMODE = "H" VCC threshold voltage 29 VtHRESL 4.3 (2.86) 4.2 level for /RESET (VMODE = "L") 350 Hysteresis of /RESET VMODE = "H" 29 HYSRESth 70 0.2 4.3 (220) level (VMODE = "L")(4) Length of pulse at (5) 5 tres 6800 4.4 /RESET pin Length of short pulse at (5) 5 tresshort 200 4.5 /RESET pin Wait for the first WD (5) 5 td 6800 4.6 trigger Time for VCC < VtHRESL (4) 29 tdelayRESL 0.5 2 4.7 before activating /RESET Resistor defining internal 4.8 bias currents for watchdog 3 RRWD 10 91 oscillator Watchdog oscillator 4.9 RRWD = 33 k 3 TOSC 11.09 13.55 period Watchdog oscillator 16 24 4.10 period with internal TOSC_start resistor 0.3 x Watchdog input 4.11 6 VILWD VVCC low-voltage threshold 0.7 x Watchdog input 4.12 6 VIHWD VVCC high-voltage threshold * Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on T100; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc 11. See Figure 5-4 on page 9 "Definition of Bus Timing Parameters" Unit Type*
V V
A A
V mV V V T100 T100 T100 s k s s V V
A A A A A A A C D A A A A
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10. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 150C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max Hysteresis of watchdog 4.13 1 6 VhysWD input voltage threshold 980 x (5) t1 4.14 Close window TOSC 780 x (5) t2 4.15 Open window TOSC Output low-voltage of 5 VOLRES 0.4 4.16 At IOLRES = 1 mA /RESET Internal pull-up resistor at 5 10 15 4.17 5 RPURES pin /RESET 5 High Voltage Serial Interface Normal mode; 5.1 Low-level output current 13 ILRX 4 VSIO = 0V, VRX = 0.4V Normal mode; VSIO = VBAT 13 IHRX 4 5.2 High-level output current VRX = VCC - 0.4V 0.9 x Driver recessive output 8 VSIOrec 5.3 VTXD = 0V; ISIO = 0 mA VBAT voltage Driver dominant voltage VVAT = 7.3V 8 V_LoSUP 5.4 1.2 Rload = 500 VBUSdom_DRV_LoSUP Driver dominant voltage VVAT = 18V 8 V_HiSUP 2 5.5 Rload = 500 VBUSdom_DRV_HiSUP Driver dominant voltage VVAT = 7.3V 8 V_LoSUP_1k 0.6 5.6 Rload = 1000 VBUSdom_DRV_LoSUP Driver dominant voltage VVAT = 18V 0.8 5.7 8 V_HiSUP_1k_ Rload = 1000 VBUSdom_DRV_HiSUP The serial diode is 20 30 60 5.8 Pull up resistor to VS 8 RLIN mandatory 5.9 Current limitation VBUS = VBAT_max 8 IBUS_LIM 50 250 Input leakage current at Input leakage current the receiver including driver off -1 5.10 8 ISIO_PAS_dom pull-up resistor as VSIO = 0V VBAT = 12V specified Driver off Leakage current SIO 8V < VBAT < 18V 5.11 8 ISIO_PAS_rec 30 recessive 8V < VSIO < 18V VSIO VBAT * Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on T100; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc 11. See Figure 5-4 on page 9 "Definition of Bus Timing Parameters" Unit V Type* A A A V k A D
mA mA V V V V V k mA mA
D D A A A A A D A A
A
A
17
4931E-AUTO-01/08
10. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 150C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max Leakage current at ground loss Control unit disconnected GNDDevice = VS 8 ISIO_NO_gnd 5.12 from ground VBAT =12V -1 1 Loss of local ground must 0V < VSIO < 18V not affect communication in the residual network Node has to sustain the current that can flow VBAT disconnected 100 5.13 under this condition. Bus VSUP_Device = GND 8 ISIO must remain operational 0V < VSIO < 18V under this condition Center of receiver VSIO_CNT = 8 VSIO_CNT 5.14 0.475 VS 0.5 VS 0.525 VS (Vth_dom + Vth_rec)/2 threshold 5.15 Receiver dominant state VEN = 5V 8 VSIOdom 0.4 VS 8 VSIOrec 0.6 VS 5.16 Receiver recessive state VEN = 5V 5.17 Receiver input hysteresis VHYS = Vth_rec - Vth_dom 8 VSIOhys 0.1 VS 0.175 VS THRec(max) = 0.744 x VBAT THDom(max) = 0.581 x VBAT 5.18 Duty cycle 1 8 D1 0.380 VBAT = 7.3V to 18V tBit = 50 s D1 = tbus_rec(min) / 2 x tBit(11) THRec(min) = 0.422 x VBAT THDom(min) = 0.284 x VBAT 5.19 Duty cycle 2 8 D2 0.600 VBAT = 7.3V to 18V tBit = 50 s D2 = tbus_rec(max) / 2 x tBit(11) Propagation delay of 5.20 8 trx_pd 6 trec_pd = max(trx_pdr, trx_pdf)(11) receiver Symmetry of receiver 8 trx_sym -2 +2 5.21 trx_sym = trx_pdr - trx_pdf(11) propagation delay 6 Control Inputs DIR, PWM, WD, TX 0.3 x Input low-voltage 6.1 VIL VVCC threshold 0.7 x Input high-voltage 6.2 VIH VVCC threshold (6) 6.3 Hysteresis HYS 0.7 * Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on T100; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc 11. See Figure 5-4 on page 9 "Definition of Bus Timing Parameters" Unit Type*
mA
A
A
A
V V V V
A A A A
A
A
s s
A A
V V
A A A
18
ATA6824
4931E-AUTO-01/08
ATA6824
10. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 150C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max 6.4 Pull-down resistor DIR, PWN, WD, TX RPD 25 50 100 100 6.5 Rise/fall time trf 7 Charge Pump VVBAT 7.1 Charge pump voltage Load = 0A 21 VCP + VVG Load = 3 mA, VVBAT 7.2 Charge pump voltage 21 VCP + VVG - 1 CCP = 100 nF Period charge pump 9 11 7.3 T100 oscillator CP load current in VG 100 7.4 Load = 0A IVGCPz without CP load CP load current in VG with Load = 3 mA, 3.3 7.5 IVGCP CP load CCP = 100 nF 8 H-bridge Driver Low-side driver HIGH 8.1 VLxH VVG output voltage ON-resistance of sink RDSON_LxL, 20 8.2 x = 1, 2 stage of pins L1, L2 ON-resistance of source RDSON_LxH, 20 8.3 x = 1, 2 stage of pins L1, L2 Output peak current at ILxL, 8.4 pins L1, L2, switched to VLx = 3V 100 x = 1, 2 LOW Output peak current at ILxH, 8.5 pins L1, L2, switched to VLx = 3V -100 x = 1, 2 HIGH Pull-down resistance at RPDLx 30 100 8.6 x = 1, 2 pins L1, L2 ON-resistance of sink RDSON_HxL, 20 8.7 VSx = 0 x = 1, 2 stage of pins H1, H2 RDSON_HxH, ON-resistance of source 20 8.8 VSx = VVBAT x = 1, 2 stage of pins H1, H2 VVBAT = 13.5V Output peak current at IHxL, 8.9 V = VVBAT 100 pins Hx, switched to LOW Sx x = 1, 2 VHx = VVBAT + 3V * Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on T100; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc 11. See Figure 5-4 on page 9 "Definition of Bus Timing Parameters" Unit k ns Type* D D
V V s A mA
A A A D A
V mA
D A A D
mA k mA
D A A A D
19
4931E-AUTO-01/08
10. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 150C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max VVBAT = 13.5V Output peak current at IHxH, -100 8.10 V = VVBAT x = 1, 2 pins Hx, switched to HIGH Sx VHx = VVBAT + 3V Static high-side switch VSx = 0V VHxL, 8.11 0.3 output low-voltage pins Hx IHx = 1 mA x = 1, 2 Static high-side switch VVBAT + VVBAT + ILx = -10 A 8.12 output high-voltage pins VHxHstat1(7) (PWM = static) VVG - 1 VVG H1, H2 Sink resistance between 3 10 RHxsleep 8.13 Hx and ground in Sleep mode Dynamic Parameters Dynamic high-side switch CHx = 5 nF VVBAT + VVBAT + VHxHdyn1 8.14 output high-voltage pins CCB = 100 nF VVG - 1 VVG fPWM = 20 kHz H1, H2 Propagation delay time, Figure 5-5 on page 12 8.15 low-side driver from high tLxHL 0.5 VVBAT = 13.5V to low Propagation delay time, 0.5 + tCC 8.16 low-side driver from low to tLxLH high VVBAT = 13.5V tLxf 8.17 Fall time low-side driver 0.5 CGx=5 nF 8.18 Rise time low-side driver tLxr 0.5 Propagation delay time, Figure 5-5 on page 12 0.5 8.19 high-side driver from high tHxHL VVBAT = 13.5V to low Propagation delay time, 8.20 high-side driver from low tHxLH 0.5 + tCC to high VVBAT = 13.5V, 8.21 Fall time high-side driver 0.5 tHxf CGx = 5 nF 8.22 Rise time high-side driver tHxr 0.5 (8) tCC 10 8.23 Cross conduction time 5 8.24 External resistor RCC 5 8.25 External capacitor CCC * Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on T100; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc 11. See Figure 5-4 on page 9 "Definition of Bus Timing Parameters" Unit mA V V Type* D D D
k
D
V
A
s
A
s s s s
A A A A
s s s s k nF
A A A A D D
20
ATA6824
4931E-AUTO-01/08
ATA6824
10. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 18V and for -40C ambient 150C unless stated otherwise. No. Parameters Test Conditions Pin Symbol Min Typ Max RON of tCC switching 8.26 100 RONCC transistor 0.653 x 0.667 x 0.68 x Switching level of tCC 8.27 Vswtcc comparator VVCC VVCC VVCC Short circuit detection (9) VSC 3.5 4 4.5 8.28 voltage Short circuit detection (10) tSC 5 10 15 8.29 time 9 Diagnostic Outputs DG1, DG2, DG3 9.1 Low level output current VDG = 0.4V(6) IL 4 IH 4 9.2 High level output current VDG = VCC - 0.4V(6) * Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. DIR, PWM = high 2. The use of X7R material is recommended 3. For higher values, stability at zero load is not guaranteed 4. Tested during qualification only 5. Value depends on T100; function tested with digital test pattern 6. Tested during characterization only 7. Supplied by charge pump 8. See section "Cross Conduction Time" 9. Voltage between source-drain of external switching transistors in active case 10. The short-circuit message will never be generated for switch-on time < tsc 11. See Figure 5-4 on page 9 "Definition of Bus Timing Parameters" Unit V V s Type* D D A A
mA mA
D D
21
4931E-AUTO-01/08
11. Ordering Information
Extended Type Number ATA6824-PHQW Package QFN32 Remarks Pb-free
12. Package Information
Package: QFN 32 - 7 x 7 Exposed pad 4.7 x 4.7 Dimensions in mm Not indicated tolerances 0.05 0.90.1 0.05-0.05 32 1 24 25 32 1
technical drawings according to DIN specifications +0
7 4.7
8 0.3 0.6
17 16 0.65 nom. 4.55 9
8
Drawing-No.: 6.543-5097.01-4 Issue: 1; 24.02.03
22
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4931E-AUTO-01/08
ATA6824
13. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History * Section 5.2 "5V/3.3V VCC Regulator" on pages 6 to 7 changed * Section 5.4 "High Voltage Serial Interface" on page 9 changed * Section 10 "Electrical Characteristics" numbers 4.1a and 4.3 on page 16 changed * * * * * * * * * * * * * * Put datasheet in a new template Section 1 "Description" on page 1 changed Figure 1-1 "Block Diagram" on page 2 changed Figure 2-1 "Pinning QFN32" on page 3 changed Table 2-1 "Pin Description" on pages 3 to 4 changed Table title Table 4-1 renamed Section 5.1.1 "Power Supply" on page 5 changed Section 5.1.3 "Temperature Supervisor" on page 6 changed Section 5.3 "Reset and Watchdog Management" on page 6 changed Section 5.4 "High Voltage Serial Interface" on page 8 changed Section 6 "Absolute Maximum Ratings" on page 13 changed Section 8 "Operating Range" on page 14 changed Section 9 "Noise and Surge Immunity" on page 14 changed Section 10 "Electrical Characteristics" on pages 15 to 21 changed
4931E-AUTO-01/08
4931D-AUTO-04/07
23
4931E-AUTO-01/08
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4931E-AUTO-01/08

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